Red Hat's Marcin Juszkiewicz reveals that current RISC-V SoCs are up to 5x slower than x86_64 for compiling Fedora packages like Binutils. We analyze the benchmark data, explore next-gen hardware like Milk-V Titan, and discuss the critical infrastructure hurdles RISC-V must overcome to become a primary Fedora architecture. Will the performance catch up?
The promise of RISC-V is undeniable: an open-standard Instruction Set Architecture (ISA) poised to democratize processor design. However, for the developers and engineers integrating this architecture into the broader Linux ecosystem, the current reality is a waiting game.
The friction point? Compile times that are not just slower, but an order of magnitude behind established players like x86_64 and AArch64. This performance bottleneck raises a critical question: Is the RISC-V ecosystem ready for prime time in mainstream distributions like Fedora Linux?
Recent benchmarks and developer insights, particularly from Red Hat, paint a clear picture of the current state of play. While the architecture's potential is vast, its present-day hardware is struggling to keep pace with the demanding task of building software packages, a foundational process for any operating system.
The Hard Data: Quantifying the RISC-V Compile-Time Lag
To understand the scale of the challenge, we must move beyond generalities and examine specific, reproducible metrics. Marcin Juszkiewicz, a Red Hat engineer with extensive expertise in ARM64 Linux, has been rigorously documenting RISC-V package builds for Fedora.
His findings, shared in a recent blog post aptly titled "RISC-V is sloooow," provide a stark quantitative look at the current state of affairs.
Using the compilation of GNU Binutils (a critical collection of binary tools) as a benchmark, the performance disparities are striking:
i686 (32-bit x86): 25 minutes
x86_64 (64-bit): 29 minutes (with Link-Time Optimizations - LTO enabled)
AArch64 (ARM64): 36 minutes
POWER PPC64LE: 46 minutes
RISC-V (RV64): 143 minutes (LTO disabled to prevent even longer build times)
The data reveals that compiling the same software on current RISC-V silicon takes nearly five times longer than on a standard x86_64 system. Even more telling is the comparison with POWER, a niche enterprise architecture, which completes the task in less than a third of the time.
The LTO Compromise
A critical nuance in this data is the status of Link-Time Optimizations (LTO). On x86_64 and AArch64, LTO is a standard compiler feature that improves runtime performance by performing optimizations across object files during the linking phase. However, on RISC-V, enabling LTO exacerbates an already protracted build process.
Developers are currently forced to disable it as a pragmatic, albeit suboptimal, trade-off to keep build times manageable. This means that not only are the builds slower, but the resulting binaries may not be as performance-optimized as they could be.
The Hardware Bottleneck: Why Current RISC-V SoCs Struggle
The root cause of these "terrible build times," as Juszkiewicz describes them, lies in the current generation of RISC-V System-on-Chips (SoCs). Unlike the mature, performance-tuned cores from Intel, AMD, and even ARM, the first wave of high-profile RISC-V hardware prioritizes low power consumption and edge applications over raw, sustained throughput.
Key limiting factors include:
Lower Clock Speeds: RISC-V SoCs typically operate at lower frequencies than their x86/ARM counterparts.
Simpler Core Microarchitectures: The out-of-order execution pipelines and branch prediction units are less sophisticated, directly impacting compiler performance, which is a highly complex sequence of operations.
Memory Subsystem Limitations: Compiling large codebases like Binutils or LLVM is memory-intensive. Limited memory bandwidth and higher latency on current RISC-V platforms create a significant bottleneck.
The Emulation Compromise: QEMU to the Rescue?
Faced with painfully slow physical hardware, developers have turned to virtualization. By leveraging QEMU (Quick Emulator), it's possible to create emulated RISC-V environments on powerful x86_64 servers. This approach offers a temporary workaround by harnessing the vastly superior performance of existing infrastructure.
For instance, Juszkiewicz notes that using 80 emulated RISC-V cores can compile the massive LLVM compiler suite in approximately four hours. In contrast, a physical Banana Pi BPI-F3 (powered by a current-gen RISC-V SoC) would take more than ten hours for the same task.
While this demonstrates the agility of the open-source tooling, it is not a viable long-term solution. Emulation introduces overhead and is fundamentally a stopgap measure to simulate an ecosystem that doesn't yet physically exist at scale.
The Road Ahead: Next-Gen Hardware and the Fedora 44 Plan
The community is not standing still. The path forward involves a multi-pronged strategy centered on next-generation silicon and updated infrastructure.
Promising Hardware on the Horizon
Juszkiewicz highlights two specific upcoming platforms that offer a glimmer of hope:
Milk-V Titan (with UltraRISC UR-DP1000 SoC): This platform is expected to provide a significant performance uplift and crucially, support up to 64 GB of RAM, addressing a major memory limitation.
SpacemiT K3-based Systems: These also promise improved performance, though currently capped at 32 GB of RAM.
These new systems are viewed as "an improvement, but not the final solution." They represent an evolutionary, not revolutionary, step. The true target is hardware that can integrate into a standard data center environment—"rackable and manageable like any other boring server."
Fedora's Pragmatic Roadmap
The Fedora RISC-V team is proceeding with a cautious, iterative plan. The immediate focus is on building Fedora Linux 44. Key elements of this strategy include:
Kernel Unification: Moving towards a single, consistent kernel image across all builders to simplify management and debugging.
LTO Remains Disabled: For the foreseeable future, Link-Time Optimizations will stay disabled to keep build times within acceptable bounds.
Targeted Hardware Allocation: There are plans to assign the most resource-intensive ("heavier") packages specifically to the new, faster builders once they are deployed.
This approach acknowledges the current hardware limitations while laying the groundwork for a future where RISC-V can become a "primary architecture" in Fedora Linux.
Conclusion: The Infrastructure Imperative
The journey of RISC-V from an exciting open ISA to a primary, first-class citizen in distributions like Fedora is currently bottlenecked by hardware performance. The data from Red Hat's Marcin Juszkiewicz serves as a crucial reality check: while the software ecosystem is adapting, it cannot outrun the limitations of physical silicon.
For RISC-V to cross the chasm from enthusiast and embedded applications to the data center and developer desktops, the next generation of hardware must deliver a dramatic leap in compile-time performance.
The goal is clear: to build the binutils package in under one hour, with LTO enabled, on a server that fits seamlessly into existing infrastructure racks. Until that hardware arrives, the promise of a fully open computing future will remain just that—a promise, waiting to be compiled into reality.
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