FERRAMENTAS LINUX: Resultados da pesquisa RISC-V

Mostrando postagens classificadas por relevância para a consulta RISC-V. Ordenar por data Mostrar todas as postagens

domingo, 20 de julho de 2025

Debian 13.0 "Trixie" Officially Supports RISC-V: What You Need to Know

Debian 13.0 "Trixie" marks a historic milestone with official RISC-V 64-bit support. Discover supported hardware, performance challenges, and future prospects for this groundbreaking Linux architecture.

Qualcomm’s RISC-V RAS Breakthrough: Paving the Way for Enterprise-Grade Linux Servers

Qualcomm leads the charge in enterprise-ready RISC-V with its inaugural Linux kernel patch series for Reliability, Availability & Serviceability (RAS) support. This comprehensive guide explores the groundbreaking RERI specification, its critical role for future RISC-V servers, and what successful testing means for data center adoption. Read the full technical analysis.

RISC-V Security Hardening: Linux Kernel 6.19 Patches Critical Speculative Execution Vulnerability

RISC-V architecture faces Spectre-like speculative execution vulnerabilities. Learn how Linux kernel 6.19-rc5 patches critical syscall side-channel attacks, mirroring x86/ARM64 security. Explore RISC-V security trends, microarchitectural hardening, and implications for high-performance computing, edge devices, and secure CPU design.

Canonical Raises RISC-V Requirements: Ubuntu 25.10 to Mandate RVA23 Profile Support

Canonical confirms Ubuntu 25.10 will require RISC-V RVA23 support, dropping legacy hardware. Learn what this means for developers, compatible boards, and upgrade paths for RISC-V users on Ubuntu Linux.

NVIDIA Expands CUDA Support to RISC-V: A Game-Changer for Data Centers and HPC

NVIDIA confirms CUDA support for RISC-V processors, a major leap for AI and data centers. Learn how this impacts AMD ROCm, cloud computing, and the future of parallel processing in our in-depth analysis.

Framework Computer Inc. Anuncia Parceria com DeepComputing para Desenvolver Placa-Mãe RISC-V para o Framework Laptop 13

A Framework Computer Inc. anunciou hoje uma colaboração inovadora com a DeepComputing para desenvolver uma placa-mãe RISC-V dedicada ao Framework Laptop 13.

Qualcomm Xqci RISC-V Extension Graduates from Experimental in LLVM 22: A Strategic Leap for Embedded Processing

The Qualcomm Xqci RISC-V vendor extension has officially shed its 'experimental' label in LLVM 22, marking a pivotal advancement for embedded systems development. This deep dive explores the extension's technical specifications, its impact on microcontroller interrupt handling and memory access, and what Qualcomm's strategic investments in RISC-V, including the Ventana acquisition, signal for the future of compute. Unpack the implications for engineers and the semiconductor industry.

GlobalFoundries Acquires MIPS: A Strategic Move to Accelerate RISC-V Innovation

GlobalFoundries acquires MIPS to scale RISC-V innovation, combining semiconductor manufacturing prowess with CPU architecture expertise. Discover how this deal reshapes the future of intelligent computing.

Andes Voyager RISC-V Development Board: A New Contender for High-Performance Computing

Discover the Andes Voyager RISC-V development board featuring a quad-core AX45MP CPU, PCIe 4.0, and NX27V vector processor. With mainline Linux support in progress, it’s a powerful platform for AI, HPC, and embedded systems. Explore its potential today.

GNU/Hurd no RISC-V: Será Essa a Virada Que o Kernel Livre Precisa?

Descubra como o GNU/Hurd pode finalmente decolar com o RISC-V! Entenda os desafios do kernel livre, o impacto do GCC 16 e quais placas suportarão o sistema. Será essa a virada que o Hurd precisava?

RISC-V Zalasr ISA Extension: A Deep Dive into Linux Kernel Integration and Performance Implications

Explore the integration of RISC-V's Zalasr ISA extension into the Linux kernel. This guide covers the technical specs, performance benefits for atomic operations, current development status, and what it means for the future of high-performance RISC-V computing.

GCC 16 Enhances RISC-V Compiler Optimization with Improved -march Handling

GCC 16’s new -march handling for RISC-V, led by Ventana Micro’s Robin Dapp, simplifies CPU-specific compilation. Learn how this patch boosts developer productivity and attracts premium ads in compilers, RISC-V hardware, and embedded systems.

The Strategic Shift: GlobalFoundries Acquires Synopsys ARC Processor IP to Fortify MIPS Portfolio

GlobalFoundries strengthens its semiconductor IP arsenal with the acquisition of Synopsys' ARC & ARC-V Processor IP. Discover the strategic implications for the RISC-V ecosystem, embedded systems design, and the global foundry landscape. Analysis of market consolidation and future compute architectures.

Mainstream Linux Embraces RISC-V: PowerVR GPU Support Lands in Kernel 6.18

Linux 6.18 kernel mainstream support for Imagination PowerVR BXM-4-64 GPU on RISC-V architecture, specifically for Alibaba T-HEAD TH1520 SoC. Discover the impact on SBCs like Lichee Pi 4A, driver improvements, and what this means for open-source graphics on emerging RISC-V hardware.